The driving circuit of a thin film transistor liquid crystal display (TFT-LCD) consists of a gate driving circuit and a data driving circuit. Generally, the gate driving circuit opens a row of pixels firstly, the data driving circuit charges this row of pixels, then the gate driving circuit closes this row of pixels and opens a next row of pixels, the data driving circuit charges the opened next row of pixels again. Each row of pixels is charged successively so as to realize display of the whole TFT-LCD.
At present, there is an existing shift register, its circuit structure is as shown in FIG. 1, in the first phase t1 during operation of the shift register: the signal inputted by the input signal terminal INPUT is of a high level, M1 is turned on, the node PU is at a high level, the capacitor C is charged, and M3 is turned on, the signal inputted by the clock signal input terminal CLK is of a low level, the signal output terminal is at a low level; in the second phase t2: the signal inputted by the input signal terminal INPUT is of a low level, M1 is turned off, the capacitor C discharges the node PU, the node PU remains at a high level, M3 remains ON, the signal inputted by the clock signal input terminal CLK is of a high level, the signal output terminal is at a high level; in the third phase t3: the signal inputted by the reset signal input terminal RESET is of a high level, M2 is turned on, the node PU is at a low level, M3, M6 and M8 are turned off, M5 and M7 remain ON, the node PD is of a high level, M4 and M9 are turned on, the signal output terminal is at a low level.
However, as shown in FIG. 2, when the signal input terminal INPUT inputs a high level signal, the PU point at one terminal of the capacitor C rises, such that the other terminal of the capacitor couples noise, thereby resulting in existence of noise in the signal outputted by the signal output terminal OUTPUT; moreover, the signal output terminal OUTPUT is connected with the clock signal input terminal CLK through M3, since the driving capability of the clock signal input terminal CLK is relatively poor, when there is a relatively large load, distortion may easily occur to the signal output terminal OUTPUT.